Field of the Invention
The present disclosure relates to a display device. More particularly, the disclosure related to a display device which adopts a design for suppressing occurrence of problems caused by electrostatic charge generated during manufacturing and/or testing of the display device, and a method for manufacturing the same.
Description of the Related Art
Electronic devices employ various types of flat panel displays, including but not limited to, a liquid crystal display, a plasma display, a field emission display, an electrophoretic display and an organic light emitting diode display to present visual information.
A display device is configured to convert an image signal input from the outside into a data voltage and display an image on a plurality of pixels in response to the image signal depending on the data voltage. Such a display device includes a substrate on which a circuit including a thin film transistor (TFT), a line, and pads connected with drive integrated circuits (D-ICs) for driving the display device is formed. Such a substrate is called an “array substrate” or a “backplane”.
Electric charge (electrostatic) may be generated while carrying out various processes for manufacturing the array substrate of the display device. For example, High-Pressure Micro Jet (HPMJ) or triboelectrification processes can cause electric charges to build up on or around the array substrate. A dry etching process and various other patterning processes can also generate electrostatics charges, which may be introduced to the array substrate through various routes. The electrostatic charges introduced to the array substrate may be trapped in various organic/inorganic layers in the display device, and affect electrical properties of various components of the array substrate such as the thin-film-transistors, resulting in display defects.
Such a problem is particularly difficult to deal with if the active area of the display device is divided into a plurality of chip-on-glass (COG) blocks, in which each of the COG blocks are driven by a discrete drive integrated circuit (D-IC) or a discrete set of drive integrated circuits. As the amount of trapped electric charges is different at different parts of the organic/inorganic layers, some COG blocks may be more heavily affected by the trapped electric charges than other COG blocks, creating electrical property differences between the COG blocks. Such differences of electrical properties between the COG blocks can result in visual differences between the parts of an image rendered by different COG blocks.
In order to improve such defects, various additional processes may be performed. For example, as for an array substrate implemented with a thin-film transistor (TFT) that uses a silicon semiconductor as an active layer, additional processes for doping a hole or a plasma process may be further performed in order to recover or otherwise improve the electrical properties of the TFT. On the contrary, additional processes for recovering or improving the electrical properties are limited for an array substrate implemented with oxide semiconductor transistor. For instance, doping the oxide semiconductor of the TFTs for closing the gap between the threshold voltages of the TFTs in different COG blocks might require shifting the threshold voltage to an undesired level. Further, high temperature processes may cause oxygen vacancies in the oxide semiconductor. Accordingly, a new structural design is needed for minimizing electrical and visual differences between the COG blocks resulting from electrostatic charges introduced during a manufacturing process of the display device.